With the advent of semiconducting 2D transition metal dichalcogenides (TMDs), field-effect transistors (FETs) can be scaled down even further, offering promising possibilities for retaining Moore's law (Figure 1a). Conventionally, bulk semiconductors are used in the channel of standard CMOS technology, but these cannot be scaled below 5 nm in thickness without posing substantial problems relating to variance, surface roughness, and dangling bonds, which reduce charge carrier mobility (Figure 1a, inset). However, using 2D semiconductors (such as TMDs), which maintain their desirable electronic properties even at the limit of a single atomic layer (i.e., monolayer with thickness 1 nm), it is possible to fabricate sub-10 nm channel length FETs with well-controlled electrostatics and suitable mobilities. Since complementary n-type and p-type transistors are used in CMOS technology to accomplish logic functions, both n-type and p-type MOS transistors are required to scale CMOS technology to its optimum capability with 2D materials. While substantial efforts have been dedicated to improving 2D NMOS devices (e.g., using MoS2 semiconducting channels), the performance of 2D PMOS FETs has fallen behind. Research at the Ivan Sanchez Esqueda laboratory (ISE lab) conducted by PhD student Naim Patoary explores improvements in ultrascaled 2D WSe2 p-type MOS transistors with emphasis on contact resistance and its role in device performance. This work analyzed WSe2 FETs with few nm high-K metal-gate (HKMG) stacks and prepared using various methods aimed at improving contact resistance (Figure 1b). Significant improvements in performance benchmarks (e.g., on-state current vs. sub-threshold swing, Figure 2) were observed against the best published results indicating a promising path towards the ultimate scaling of CMOS technology using 2D materials.
Our work prepared p-type transistors with few layer (3-5 layer) WSe2 channels. These are designed and fabricated with a high-K metal-gate (HKMG) stack featuring 8 nm of either Al2O3 or HfO2 gate dielectrics. High work function (WF) metal contacts were used to facilitate the injection and conduction of positively charged carriers (holes) into the WSe2 channels. A 3D schematic of the test structure is shown in Figure 2a.
Our gate-first HKMG process includes patterning and deposition of a Cr/Au metal gate (e-beam lithography, evaporation, and lift-off) followed by atomic-layer deposition (ALD) of the high-K dielectric (8 nm Al2O3 or HfO2). Electron beam lithography was conducted using the JEOL 6000FS at the NanoFab ASU facility to define a transfer-length method (TLM) pattern of source and drain electrodes using PMMA (Polymethyl methacrylate) as mask (SEM image of TLM structure shown in Figure 2b). The metals (Pt/Au or Pd/Au) were deposited by e-beam metal evaporation (Lesker 3) in the cleanroom facility at a rate of 2 Å/s at a pressure of 10-7 torr to ensure the uniformity of the electrode pads. Our study reports low contact resistance ~5.7 kΩ-µm, with on-state currents of ~97 µA/µm and subthreshold swing of ~140 mV/dec in FETs with channel lengths of 400 nm (Figure 2c,d). Apart from providing significant insights on emerging methods to enhance contact quality and improve performance of p-type FETs with 2D channel materials, our work presented physics-based model calculations for ballistic WSe2 devices to elucidate the performance of extremely scaled FETs towards the ultimate limit of CMOS scaling.
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Authors: Md Naim Patoary and Dr. Ivan Sanchez Esqueda