Advanced Electronics and Packaging

About

The Advanced Electronics and Packaging Core facility located in the ASU MacroTechnology Works building provides comprehensive electronics capabilities bridging the high-risk, resource-intensive gap between innovation and product development in an information-secure environment. AEP Core offers backplane electronics design, fabrication, test and integration capabilities, and operates dedicated pilot line toolsets for technology development focused on fanout wafer level packaging.

Located in the ASU Research Park, the ASU MacroTechnology Works building houses more than 43,500 square feet of Class 1,000 and Class 10,000 clean room space and an additional 22,000 square feet of wet/dry lab space housed in a 250,000 square foot total building footprint. AEP Core occupies about one-third of the usable cleanroom space in the MacroTechnology Works building. A wide range of processing and metrology equipment commonly found in a wafer scale packaging facility and is available for use at AEP Core.

The available metrology equipment set includes defect measurements, scanning acoustic microscopy, bow/warp measurements, ellipsometry, reflectometry, profilometry, infrared spectroscopy, scanning electron microscopy, four-point probe, contact angle, film stress and defect analysis.

The processing equipment set includes photolithography, acid and base etching, reactive ion etching, plasma enhanced chemical vapor deposition, sputter deposition, thermal and ion beam assisted evaporation, substrate cleaning, and packaging panelization equipment. AEP can also assist with photomask design and device characterization (I-V sweeps).

Testimonials

We do nontraditional semiconductors. Where the majority of companies in the United States are doing semiconductors on silicon wafers, we are doing semiconductors on large glass panels and flexible substrates. ASU has critical technology that has been extremely vital to our ability to advance that.

Lindsay Pack CEO, InnovaFlex