About

The Advanced Electronics and Packaging facility provides comprehensive electronics capabilities bridging the high-risk, resource-intensive gap between innovation and product development in an information-secure environment. AEP offers backplane electronics design, fabrication, test and integration capabilities, and operates dedicated pilot line toolsets for technology development and technology demonstrator production.

AEP began as the Flexible Electronics and Display Center, a public-private consortium intended to bring flexible displays and flexible electronics to production capability. The FEDC was very successful over the 15 years of its existence at pushing the boundaries of flexible electronics. Many of the staff from the FEDC remain on hand to help guide new projects from the design phase through full prototyping.

Located in the ASU Research Park, AEP houses more than 43,500 square feet of Class 1,000 and Class 10,000 clean room space and an additional 22,000 square feet of wet/dry lab space housed in a 250,000 square foot total building footprint. Many of the resources utilized by the FEDC in the production of flexible displays and flexible electronics are now available through AEP. A wide range of processing and metrology equipment commonly found in a thin film transistor FAB is available for use at AEP.

The available metrology equipment set includes defect measurements, scanning acoustic microscopy, bow/warp measurements, ellipsometry, reflectometry, profilometry, infrared spectroscopy, scanning electron microscopy, four-point probe, contact angle, film stress and defect analysis.

The processing equipment set includes photolithography, acid and base etching, reactive ion etching, downstream plasma etching, plasma enhanced chemical vapor deposition (PECVD), sputter deposition, thermal and ion beam assisted evaporation, substrate cleaning, packaging panelization equipment and temporary flexible substrate bonding with adjustable adhesion strength to eliminate need for de-bonding equipment, chemicals or post de-bond cleaning. AEP can also assist with photomask design and device characterization (I-V sweeps).

Testimonials

We do nontraditional semiconductors. Where the majority of companies in the United States are doing semiconductors on silicon wafers, we are doing semiconductors on large glass panels and flexible substrates. ASU has critical technology that has been extremely vital to our ability to advance that.

Lindsay Pack CEO, InnovaFlex